1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to forming a FinFET using a single spacer, double hardmask dual-epi scheme.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well-known photolithographic masking, developing, and level definition, e.g., etching, implanting, depositing, etc.
The FinFET is a transistor design that attempts to overcome the issues of short-channel effect encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL). Such effects make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel—in other words, to turn the transistor off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it is possible to wrap the gate around all but one of its sides, providing much greater electrostatic control over the carriers within it.
For FinFETs, it is desirable to be able to implant halos at the highest angle possible. As such, the gate stack needs to be as short as possible to achieve this. On the other hand, the gate stack is preferably tall so that the spacers protect the dummy gate from unwanted epi growth. However, current approaches using a tall dummy gate hardmask stack and a dual SiN spacer to form dual epi cause a large “bump” in the transition region between a N-type metal-oxide-semiconductor (NMOS) and a P-type metal-oxide-semiconductor (PMOS), which complicates the poly removal process prior to forming a replacement metal gate (RMG). As dimensions scale, dual spacers are inherently thicker and leave less room for contact. There is also less area between fins for the parasitic spacers on fin sidewalls to easily etch. Previous approaches use an oxide hardmask with a required thickness greater than 100 Å in order to have the oxide hardmask survive the epi precleans in a dilute hydrofluoric (dHF) process or equivalent oxide etch. For tight-pitch FinFETs (e.g., <60 nm), this thickness is problematic, as two hardmasks fail to leave adequate space between fins.